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GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls
August 1998 Revised December 2000
GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls
General Description
The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic levels s Variable edge rate control pin to select desired edge rate on the GTLP backplane (VERC) s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink -24mA/+24mA s B Port sink +100mA s Partitioned as two 8-bit transceivers with individual latch timing and output control but with a common clock s External pin to pre-condition I/O capacitance to high state (VCCBIAS)
Ordering Code:
Order Number GTLP16T1655MTD Package Number MTD64 Package Description 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2000 Fairchild Semiconductor Corporation
DS500172
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GTLP16T1655
Connection Diagram
Pin Descriptions
Pin Names 1OEAB 2OEAB 1OEBA 2OEBA OE 1LEAB 2LEAB 1LEBA 2LEBA VREF CLK 1A1-1A8 2A1-2A8 1B1-1B8 2B1-2B8 B Port I/O Byte 1 and Byte 2 Description A-to-B Output Enable (Active LOW) Byte 1 and Byte 2 B-to-A Output Enable (Active LOW) Byte 1 and Byte 2 Disables all I/O ports simultaneously A-to-B Latch Enable (Transparent HIGH) Byte 1 and Byte 2 B-to-A Latch Enable (Transparent HIGH) Byte 1 and Byte 2 GTLP Reference Voltage A-to-B and B-to-A Clock A Port I/O Byte 1 and Byte 2
Truth Tables
(Note 1) Inputs OEAB H L L L L L L LEAB X H H L L L L CLK X X X A X L H L H X X Output B Z L H L H B0 (Note 2) B0 (Note 3) High Impedance Transparent Transparent Registered Registered Previous State Previous State Mode

H L
Inputs OE L L L L H OEAB (Note 4) L L H H X OEBA (Note 4) L H L H X
Outputs A Port Active Z Active Z Z B Port Active Active Z Z Z
Inputs VERC VCC GND
Output Edge B Port Slow Fast
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLK. Note 2: Output level before the indicated steady state input conditions were established, provided CLK was HIGH prior to LEAB going LOW. Note 3: Output level before the indicated steady state input conditions were established. Note 4: OEAB and OEBA are byte-wide enables. Each is proceeded by a number indicating the byte controlled.
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GTLP16T1655
Functional Description
The GTLP16T1655 is a high drive (100 mA) 16-bit universal bus transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. The device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output control signals but with a common clock pin (CLK) for both transceiver words. Data flow for each word is determined by the respective latch enables (xLEAB and xLEBA), output enables (xOEAB and xOEBA) and clock (CLK). The output enables (1OEAB, 1OEBA, and 2OEAB and 2OEBA) control Byte1 and Byte2 data for the A to B and B to A directions respectively. For A-to-B data flow, the devices operate in the transparent mode when LEAB is HIGH. When LEAB transitions LOW, the A data is latched independent of CLK HIGH or LOW. If LEAB is LOW the A data is registered on the CLK LOW-to-HIGH transition. When OEAB is LOW the outputs are active. With OEAB HIGH the outputs are HIGH impedance. Data flow for the B-to-A direction is identical but uses OEBA, LEBA and CLK. Note that CLK is common to both directions and both 8-bit words. OE is also common and is used to disable all I/O ports simultaneously.
Logic Diagrams
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GTLP16T1655
Absolute Maximum Ratings(Note 5)
Supply Voltage (VCC) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 6) DC Output Sink Current into A Port IOL DC Output Source Current from A Port IOH DC Output Sink Current into B Port in the LOW State, IOL (Note 7) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC ESD Rating Storage Temperature (TSTG) 200 mA 48 mA
-0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to + 4.6V
Recommended Operating Conditions
Supply Voltage VCC Bus Termination Voltage (VTT) GTLP GTL VREF GTLP GTL Input Voltage (VI) on A Port and Control Pins on B Port HIGH Level Output Current (IOH) A Port 0.0V to VCC 0.0V to Vtt 0.87V to 1.1V 0.74V to 0.87V 1.35V to 1.65V 1.14V to 1.26V 3.0V to 3.6V
-48 mA
-24 mA +24mA +100 mA -40C to +85C
-50 mA -50 mA +50 mA >2000V -65C to +150C
LOW Level Output Current (IOL) A Port B Port Operating Temperature (TA)
Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 6: IO Absolute Maximum Rating must be observed. Note 7: VTT and Rterm can be adjusted to accommodate backplane impedances other than 50, within the boundaries of not exceeding the DC Absolute IOL ratings (200 mA). Similarly VREF can be adjusted to compensate for changes in VTT.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL VREF VIK VOH A Port B Port Others B Port Others GTLP VCC = 3.0V VCC = Min to Max (Note 9) VCC = 3.0V VOL A Port VCC = Min to Max (Note 9) VCC = 3.0V B Port VCC = 3.0V II = -18 mA IOH = -100 A IOH = -12 mA IOH = -24 mA IOL = 100 A IOL = 12 mA IOL = 24 mA IOL = 40 mA IOL = 80 mA IOL = 100 mA II A Port B Port IOFF II(hold) Except VERC A Port VCC = 3.0V VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 0 VI = VCC or 0V VI = VCC or 0V VI = VTT or GND VI or VO = 0 to VCC VI = 0.8V VI = 2.0V VI = 0 to VCC 75 -75 500 A Control Pins VCC = 3.6V VCC -0.2 2.4 2.2 0.20 0.40 0.50 0.20 0.40 0.50 10 10 10 100 A A A A V V V 0.74 1.0 Test Conditions Min VREF +0.05 2.0 0.0 VREF -0.05 0.8 1.1 -1.2 Typ (Note 8) VTT V V V V V V Max Units
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GTLP16T1655
DC Electrical Characteristics
Symbol IOZH IOZL IOZPU (Note 10) IOZPD (Note 10) ICC (vcc) ICC (Note 11) Ci A Port and A Port A Port B Port A Port B Port A Port VCC = 0 to 1.5V OE = 0 or VCC VCC = 1.5 to 0V OE = 0 or VCC A or B Ports VCC = 3.6 IO = 0 VI = V CC or GND VCC = 3.6V Inputs at VCC or GND Control Pins A Port B Port
Note 8: All typical values are at VCC = 3.3V, and TA = 25C.
(Continued)
Min Typ (Note 8) 10 10 -10 -10 50 50 55 55 55 0 1 mA 5.8 8.0 8.3 7.0 9.5 9.9 pF mA A A A A Max Units
Test Conditions VCC = 3.6V VCC = 3.6V VO = V CC VO = 1.5V VO = 0V VO = 0.4V VO = 0.5 to 3V VO = 0.5 to 3V Outputs HIGH Outputs LOW Outputs Disabled One Input at VCC-0.6 VI = VCC or 0 VI = VCC or 0 VI = VCC or 0
Control Pins A or Control
Note 9: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 10: This is specified by characterization but not tested. Note 11: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Live Insertion Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Parameter ICC (VCCBIAS) VO IO B Port B Port B Port VCC = 0 to 3V VCC = 3.0 to 3.6V VCC = 0 VCC = 0 VI (VCCBIAS) = 3.3v VI (VCCBIAS) = 3 to 3.6V OE = 3.3V OE = 0 to 3.3V VO = 0.4 -1 100 100 A Test Conditions VO = 0 to 1.2V VI (VCCBIAS) = 3 to 3.6V 1.1 Min Typ Max 5 10 Units mA A V
VCC = 0 to 3.6V VCC = 0 to 1.5V
AC Operating Requirements (GTLP)
Over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5V and Vref = 1.0V (unless otherwise noted). Parameter fMAX tWIDTH Maximum Clock Frequency Pulse Duration LE HIGH CLK HIGH or LOW tSU Setup Time Data before CLK Data before LE (CLK = X) tHOLD Hold Time Data after CLK Data after LE (CLK = X) Min 160 3.0 ns 3.0 2.5 ns 2.5 0.5 ns 0.5 Max Unit MHz
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GTLP16T1655
B to A
AC Electrical Characteristics (GTLP)
From To (Output) 160 B A 1.0 1.5 LEAB A 1.2 1.2 CLK A 1.2 1.2 OE A 1.4 1.0 OEBA A 1.2 1.0 4.7 ns 4.8 4.0 ns 3.8 4.0 ns 4.0 4.5 ns 4.0 4.9 ns 4.0 Min Typ (Note 12) MHz Max Unit
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V, VTT = 1.5V, VERC = VCC or GND (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Parameter (Input) fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLZ/HZ tPZH/ZL tPLZ/HZ tPZH/ZL
Note 12: All typical values are at VCC = 3.3V, and TA = 25C.
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GTLP16T1655
A to B
AC Electrical Characteristics (GTLP)
From To (Output) 160 A VERC = VCC A VERC = GND LEAB VERC = VCC LEAB VERC = GND CLK VERC = VCC CLK VERC = GND OE VERC = VCC OE VERC = GND OEAB VERC = VCC OEAB VERC = GND Transition Time, B outputs (0.6V to 1.3V) B B B B B B B B B B 2.6 0.8 2.0 0.7 2.6 0.8 2.2 0.7 2.8 1.0 2.3 0.8 2.7 0.6 2.1 1.0 2.6 0.6 2.0 0.6 0.7/0.7 2.0/2.5 5.7 ns 4.5 4.9 ns 4.0 5.7 ns 4.0 4.9 ns 4.0 5.7 ns 4.0 5.0 ns 4.0 5.8 ns 4.0 4.9 ns 4.0 5.8 ns 4.0 4.9 ns 3.5 ns Min Type (Note 13) MHz Max Units
Over recommended range of supply voltage and operating free air temperature, V = 1.0V, VTT = 1.5V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol (Input) fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tFALL/RISE VERC = V CC tFALL/RISE VERC = GND
Transition Time, B outputs (0.6V to 1.3V)
0.7/0.7
1.5/2.0
ns
Note 13: All Typical values are at VCC = 3.3V and TA = 25C
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GTLP16T1655
Extended Electrical Characteristics (GTLP)
Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tOSLH (Note 15) tOSHL (Note 15) tPV(HL) (Note 16) (Note 17) tOSLH (Note 15) tOSHL (Note 15) tPV(HL) (Note 16)(Note 17) tOSLH (Note 15) tOSHL (Note 15) tOST (Note 15) tPV (Note 16) tOSLH(Note 15) tOSHL (Note 15) tOST(Note 15) tPV (Note 16) CLKAB CLKAB A A B B CLKAB A A A 0.3 0.3 0.5 CLKAB B B A 0.3 0.3 0.6 A CLKAB B B 0.3 0.3 From (Input) A To (Output) B Min Typ (Note 14) 0.4 0.4 1.0 1.0 1.5 0.9 0.6 1.2 1.0 1.0 1.5 1.6 0.6 0.6 1.0 1.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max Unit
Note 14: All typical values are at VCC = 3.3V, and TA = 25C. Note 15: tOSHL/tOSLH and tOST--Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 16: tPV--Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 17: Due to the open drain structure on GTLP outputs, tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane.
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GTLP16T1655
AC Operating Requirements (GTL)
Over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2V and Vref = 0.8V (unless otherwise noted). Parameter fMAX tWIDTH tSU tHOLD Maximum Clock Frequency Pulse Duration Setup Time Hold Time LE HIGH CLK HIGH or LOW Data before CLK Data before LE (CLK = X) Data after CLK Data after LE (CLK =X) Min 160 3.0 3.0 2.5 2.5 0.5 0.5 Max Units MHz ns ns ns ns
B to A
AC Electrical Characteristics (GTL)
From To (Output) 160 B A 1.0 1.2 LEBA A 1.0 1.1 CLK A 1.0 1.1 OE A 1.5 1.2 OEBA A 1.2 1.0 4.7 4.8 4.4 4.0 4.2 4.1 4.6 4.2 4.9 4.0 ns ns ns ns Min Typ (Note 18) MHz ns Max Units
Over recommended range of supply voltage and operating free air temperature, Vref = 0.8V, VTT = 1.2V, VERC = VCC or GND (unless otherwise noted). CL = 30pF for B Port and CL = 50 pF for A Port. Parameter (Input) fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLZ/HZ tPZH/ZL tPLZ/HZ tPZH/ZL
Note 18: All Typical values are at VCC = 3.3V and TA = 25C.
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GTLP16T1655
A to B
AC Electrical Characteristics (GTL)
From To (Output) 160 A VERC = VCC A VERC = GND LEAB VERC = VCC LEAB VERC = GND CLK VERC = VCC CLK VERC = GND OE VERC = VCC OE VERC = GND OEAB VERC = VCC OEAB VERC = GND Transition Time, B outputs (0.6V to 1.3V) B B B B B B B B B B 2.2 1.0 1.5 0.9 2.2 1.0 1.7 0.9 2.8 1.0 2.3 1.0 2.5 0.8 1.7 0.9 2.2 0.8 1.7 0.9 0.7/0.7 2.0/2.5 5.7 ns 4.7 4.8 ns 4.0 5.7 ns 4.1 5.0 ns 4.4 5.8 ns 4.3 5.0 ns 4.3 5.8 ns 4.3 4.9 ns 4.3 5.8 ns 4.3 4.9 ns 3.8 ns Min Typ (Note 19) MHz Max Units
Over recommended range of supply voltage and operating free air temperature, VREF = 0.8V, VTT = 1.2V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol (Input) fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tFALL/RISE VERC = VCC tFALL/RISE VERC = VCC
Transition Time, B outputs (0.6V to 1.3V)
0.7/0.7
1.5/2.0
ns
Note 19: All Typical values are at VCC = 3.3V and TA = 25C.
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GTLP16T1655
Extended Electrical Characteristics (GTL)
Over recommended ranges of supply voltage and operating free-air temperature VREF = 0.8V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tOSLH (Note 21) tOSHL (Note 21) tPV(HL) (Note 22) (Note 23) tOSLH (Note 21) tOSHL (Note 21) tPV(HL) (Note 22)(Note 23) tOSLH (Note 21) tOSHL (Note 21) tOST (Note 21) tPV (Note 22) tOSLH(Note 21) tOSHL (Note 21) tOST(Note 21) tPV (Note 22) CLKAB CLKAB A A B B CLKAB A A A 0.3 0.3 0.5 CLKAB B B A 0.3 0.3 0.6 A CLKAB B B 0.3 0.3 From (Input) A To (Output) B Min Typ (Note 20) 0.4 0.4 1.0 1.0 1.5 0.9 0.6 1.2 1.0 1.0 1.5 1.6 0.6 0.6 1.0 1.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max Unit
Note 20: All typical values are at VCC = 3.3V, and TA = 25C. Note 21: tOSHL/tOSLH and tOST--Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTL outputs could vary on the backplane due to the loading and impedance seen by the device. Note 22: tPV--Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTL outputs could vary on the backplane due to the loading and impedance seen by the device. Note 23: Due to the open drain structure on GTL outputs, tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane.
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GTLP16T1655
Test Circuits and Timing Waveforms
Test Circuit for A Outputs Test Circuit for B Outputs
Test tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S Open 6V GND
Note A: C L includes probes and Jig capacitance. Note B: For B Port, C L = 30 pF is used fort worst case.
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Setup and Hold Times
Voltage Waveform - Pulse Width
Voltage Waveform - Enable and Disable Times
Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output Output Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output
Input and Measure Conditions A or LVTTL Pins VinHIGH VinLOW VM VX VY 3.0 0.0 1.5 VOL + 0.3V VOH - 0.3V B or GTLP Pins 1.5 0.0 1.0 N/A N/A
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = t FALL = 2 ns, ZO = 50 The outputs are measured one at a time with one transition per measurement
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GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls
Physical Dimensions inches (millimeters) unless otherwise noted
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD64
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 13 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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